1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly to a structure of a boosted power supply generating circuit.
2. Description of the Background Art
Conventionally, for a semiconductor integrated circuit such as a DRAM (Dynamic Random Access Memory), a boosted power supply has been widely used to eliminate the influence of a threshold voltage of a transistor. In the DRAM, a boosted power supply Vpp is primarily used as a word line voltage or the like.
FIG. 14 is a block diagram showing a boosted power supply generating circuit 500 (hereinafter referred to as a Vpp generating circuit).
Vpp generating circuit 500 includes a detector circuit 100, a ring oscillator circuit 200, and a pump circuit 300.
Detector circuit 100 detects any decrease in its voltage below a prescribed level due to current consumption of the semiconductor integrated circuit or the like for generating a signal "PHgr"1 in generating Vpp.
An exemplary ring oscillator circuit 200 is shown in FIG. 15.
Ring oscillator circuit 200 includes an NAND circuit 201, a delay circuit 206 having inverters 202 to 205 connected in series, and an inverter 207.
Ring oscillator circuit 200 receives signal "PHgr"1 for repeatedly generating pulse signal "PHgr"2.
An exemplary pump circuit 300 is shown in FIG. 16.
Pump circuit 300 includes capacitors 301, 302, and 303, an inverter 304, and N channel transistors 305, 306, 307, and 308.
In pump circuit 300, capacitor 301 is arranged between nodes N1 and N3. N channel transistor 305 is arranged between an external power supply source Ext. Vcc (hereinafter referred to as Vcc) and node N3, having its gate connected to external power supply source Vcc. N channel transistor 306 is arranged between external power supply source Vcc and node N4, having its gate connected to node N3. N channel transistor 307 is arranged between external power supply source Vcc and node N5, having its gate connected to node N3. Inverter 304 is arranged between nodes N1 and N2. Capacitor 302 is arranged between nodes N2 and N5. Capacitor 303 is arranged between nodes N2 and N4. N channel transistor 308 is arranged between nodes N4 and N6, having its gate connected to node N5. Vpp is supplied to each portion of the circuit from node N6.
Pump circuit 300 receives output signal "PHgr"2 from ring oscillator circuit 200 for generating Vpp by a pumping operation of capacitors 301, 302, and 303.
The operation of Vpp generating circuit 500 shown in FIG. 14 will be described with reference to a time chart of FIG. 17.
Detector circuit 100 is set to output signal "PHgr"1 at xe2x80x9cLxe2x80x9d if its voltage is at a desired level (at or higher than a detection level) in generating Vpp.
Detector circuit 100 detects any decrease in Vpp below a prescribed level due to power consumption of the semiconductor integrated circuit, and outputs signal "PHgr"1 at xe2x80x9cH.xe2x80x9d
If the decrease in Vpp is detected, output signal "PHgr"1 at xe2x80x9cHxe2x80x9d is input from detector circuit 100, and therefore ring oscillator circuit 200 repeatedly outputs pulse signal "PHgr"2 at xe2x80x9cHxe2x80x9d in response to input signal "PHgr"1 at xe2x80x9cHxe2x80x9d until Vpp attains to a prescribed level by a pumping operation which will later be described (FIG. 17 shows that one pumping operation restores Vpp).
If no decrease in Vpp is detected, output signal "PHgr"1 at xe2x80x9cLxe2x80x9d is input from detector circuit 100, and therefore ring oscillator circuit 200 outputs signal "PHgr"2 at xe2x80x9cL.xe2x80x9d
At the time, in pump circuit 300, node N1 is at xe2x80x9cL,xe2x80x9d and node N2 is at xe2x80x9cHxe2x80x9d because of inverter 304.
Node N3 is precharged to a level of power supply voltage Vccxe2x88x92Vth (Vth is a threshold voltage of N channel transistor 305), and capacitor 301 is charged.
Nodes N4 and N5 are at a level of Vccxe2x88x922Vth (Vth is a threshold voltage of N channel transistors 306 and 307).
If detector circuit 100 detects any decrease in Vpp, it outputs signal "PHgr"1 at xe2x80x9cH.xe2x80x9d
Ring oscillator circuit 200 operates in response to signal "PHgr"1 at xe2x80x9cH,xe2x80x9d and outputs signal "PHgr"2 at xe2x80x9cH.xe2x80x9d
At the time, node N1 is at xe2x80x9cH,xe2x80x9d and the pumping operation of capacitor 301 brings node N3 to a level of 2Vccxe2x88x92Vth, so that N channel transistors 306 and 307 are fully turned on.
Node N2 attains from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d because of inverter 304.
Thus, although the voltage levels at nodes N4 and N5 temporarily decrease, they are precharged to the Vcc level when N channel transistors 306 and 307 are turned on.
Thus, capacitors 302 and 303 are charged to the Vcc level.
Subsequently, when output signal "PHgr"2 from ring oscillator circuit 200 attains to xe2x80x9cL,xe2x80x9d node N2 attains to xe2x80x9cHxe2x80x9d because of inverter 304.
The pumping operation of capacitors 302 and 303 causes nodes N4 and N5 to attain to the 2Vcc level.
Then, N channel transistor 308 is turned on and electric charges are supplied to node N6. As a result, the voltage level at node N6 rises.
A stress test is performed on a semiconductor integrated circuit to assure reliability, in which a high electric field is applied to an oxide film. In the above described Vpp generating circuit, reliability of capacitors 301, 302, and 303 must also be assured. In a stress test mode, the semiconductor integrated circuit is maintained in a stand-by mode and detector circuit 100 is inactivated by a Test signal shown in FIG. 14. At the time, output signals "PHgr"1 and "PHgr"2, respectively from detector circuit 100 and ring oscillator circuit 200, are both at xe2x80x9cL.xe2x80x9d Thus, in the stress test mode, nodes N1 and N2 of the pump circuit 300 are always at xe2x80x9cLxe2x80x9d and xe2x80x9cH,xe2x80x9d respectively. Accordingly, capacitors 302 and 303 are subject to weaker stress as compared with capacitor 301.
Having the above described structure, Vpp generating circuit 500 of a conventional semiconductor integrated circuit suffers from a problem that a desired level of stress cannot be applied to each capacitor in the pump circuit in a stress test mode for assuring reliability.
The present invention provides a Vpp generating circuit which ensures that a capacitor is reliably tested.
A semiconductor integrated circuit of the present invention includes: a plurality of memory cells arranged in a matrix; a memory cell array region having a plurality of word lines arranged corresponding to rows; and a plurality of bit lines arranged corresponding to columns; a pump circuit generating by a plurality of capacitors a boosted voltage supplied to the memory cell array region; and a test circuit controlling a level of stress applied to the plurality of capacitors in the pump circuit.
Preferably, the test circuit is controlled by a test signal.
Particularly, the test signal controls levels of stress applied to the plurality of capacitors.
According to the above described semiconductor integrated circuit, a desired level of stress can be applied to each capacitor in the pump circuit in a stress test mode, so that the semiconductor integrated circuit is provided with enhanced reliability.
Particularly, the test circuit controls the levels of stress applied to the plurality of capacitors simultaneously by the test signal.
According to the semiconductor integrated circuit of the present invention, desired levels of stress can be simultaneously applied to capacitors of the pump circuit in the stress test, so that the efficiency of the stress test and the reliability of the semiconductor integrated circuit increases.
Particularly, the test signal is input from an external signal pin.
Particularly, the test signal is input from an external pad.
Preferably, there is further provided a test signal generating circuit for internally generating the test signal.
Particularly, the test signal generating circuit generates a test signal in response to input from the external signal pin.
Particularly, the test signal generating circuit generates the test signal in response to input from the external pad.
According to the semiconductor integrated circuit of the present invention, the input test signal is generated from the external pad, external signal pin, or internally from test signal generating circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.